Hacker News
- Looking for Advice on how to apporach RISCV Design-Space-Exploration https://github.com/stnolting/neorv32 6 comments riscv
- A tiny and open-source (BSD) RISC-V SoC for (all!) FPGAs https://github.com/stnolting/neorv32 3 comments opensource
- Trying to compile a test program for a NEORV32 FPGA implementation. Strange issue with CSR register in assembler. Any ideas? https://github.com/stnolting/neorv32 6 comments riscv
Linking pages
- GitHub - stnolting/captouch: 👇 Add capacitive touch buttons to any FPGA! https://github.com/stnolting/captouch 17 comments
- GitHub - riscvarchive/riscv-cores-list: RISC-V Cores, SoC platforms and SoCs https://github.com/riscvarchive/riscv-cores-list 11 comments
- GitHub - suryakantamangaraj/AwesomeRISC-VResources: It contains a curated list of awesome RISC-V Resources. https://github.com/suryakantamangaraj/AwesomeRISC-VResources?tab=readme-ov-file#cores 8 comments
- GitHub - stnolting/neo430: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL. https://github.com/stnolting/neo430 7 comments
- neorv32/README.md at main · stnolting/neorv32 · GitHub https://github.com/stnolting/neorv32/blob/main/README.md 6 comments
- GitHub - stnolting/neoTRNG: 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC). https://github.com/stnolting/neoTRNG 4 comments
- GitHub - stnolting/wb_spi_bridge: 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP). https://github.com/stnolting/wb_spi_bridge 4 comments
- arl/README-VHDL.md at master · kaxap/arl · GitHub https://github.com/kaxap/arl/blob/master/README-VHDL.md 2 comments
- GitHub - stnolting/fpga_puf: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA. https://github.com/stnolting/fpga_puf 1 comment
- GitHub - stnolting/neorv32-verilog: ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL. https://github.com/stnolting/neorv32-verilog 0 comments
- GitHub - stnolting/neorv32-riscof: ✔️ Verify the NEORV32 Processor's RISC-V compatibility using RISCOF. https://github.com/stnolting/neorv32-riscof 0 comments
- GitHub - riscvarchive/riscv-cores-list: RISC-V Cores, SoC platforms and SoCs https://github.com/riscv/riscv-cores-list 0 comments
- GitHub - rdolbeau/SBusFPGA: Stuff to put a FPGA in a SBus system (SPARCstation) https://github.com/rdolbeau/SBusFPGA 0 comments
- GitHub - aolofsson/awesome-opensource-hardware: List of awesome open source hardware tools, generators, and reusable designs https://github.com/aolofsson/awesome-opensource-hardware 0 comments
- FOSDEM 2024 schedule - Open-source embedded, mobile, IoT, robotics, RISC-V, etc.. - CNX Software https://www.cnx-software.com/2024/01/24/fosdem-2024-schedule-open-source-embedded-mobile-iot-robotics-risc-v-etc/ 0 comments
Linked pages
- RISC-V International https://riscv.org/ 52 comments
- GitHub - stnolting/neoTRNG: 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC). https://github.com/stnolting/neoTRNG 4 comments
- GitHub - enjoy-digital/litex: Build your hardware, easily! https://github.com/enjoy-digital/litex 3 comments
- GitHub - stnolting/neorv32-verilog: ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL. https://github.com/stnolting/neorv32-verilog 0 comments
- GitHub - stnolting/neorv32-riscof: ✔️ Verify the NEORV32 Processor's RISC-V compatibility using RISCOF. https://github.com/stnolting/neorv32-riscof 0 comments
- [Datasheet] The NEORV32 RISC-V Processor https://stnolting.github.io/neorv32/ 0 comments
- NEORV32 — Zephyr Project Documentation https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html 0 comments
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