Hacker News
Linking pages
- Antmicro · Running Linux with Quad-core SMP in LiteX/VexRiscv on Arty A7 https://antmicro.com/blog/2020/05/multicore-vex-in-litex/ 77 comments
- GitHub - aolofsson/awesome-hardware-tools: List of awesome open source hardware tools https://github.com/aolofsson/awesome-hardware-tools 36 comments
- GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. https://github.com/stnolting/neorv32 29 comments
- GitHub - rprinz08/hBPF: hBPF = eBPF in hardware https://github.com/rprinz08/hBPF 27 comments
- FPGA: Why so few open source drivers for open hardware? - mupuf.org https://mupuf.org/blog/2020/06/09/FPGA-why-so-few-drivers/ 24 comments
- GitHub - gatecat/prjoxide: Documenting Lattice's 28nm FPGA parts https://github.com/daveshah1/prjoxide 23 comments
- GitHub - SpinalHDL/NaxRiscv https://github.com/SpinalHDL/NaxRiscv 17 comments
- GitHub - riscvarchive/riscv-cores-list: RISC-V Cores, SoC platforms and SoCs https://github.com/riscvarchive/riscv-cores-list 11 comments
- Exit MIG, Enter LiteDRAM. | BoxLambda https://epsilon537.github.io/boxlambda/exit-mig-enter-litedram/ 7 comments
- GitHub - olofk/serv: SERV - The SErial RISC-V CPU https://github.com/olofk/serv 6 comments
- neorv32/README.md at main · stnolting/neorv32 · GitHub https://github.com/stnolting/neorv32/blob/main/README.md 6 comments
- GitHub - google/CFU-Playground: Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below. https://github.com/google/CFU-Playground 4 comments
- GitHub - riscvarchive/riscv-cores-list: RISC-V Cores, SoC platforms and SoCs https://github.com/riscv/riscv-cores-list 0 comments
- GitHub - BrunoLevy/learn-fpga: Learning FPGA, yosys, nextpnr, and RISC-V https://github.com/BrunoLevy/learn-fpga/ 0 comments
- GitHub - nikitavoloboev/github-stars: Curated list of my GitHub stars https://github.com/nikitavoloboev/github-stars 0 comments
- Getting Started with ECP5 FPGAs on the Colorlight i5 FPGA Development Board | Electronics etc… https://tomverbeure.github.io/2021/01/22/The-Colorlight-i5-as-FPGA-development-board.html 0 comments
- How to Build a Trustworthy Free/Libre Linux Capable 64-bit RISC-V Computer https://insights.sei.cmu.edu/sei_blog/2019/10/how-to-build-a-trustworthy-freelibre-linux-capable-64-bit-risc-v-computer.html 0 comments
- GitHub - rdolbeau/SBusFPGA: Stuff to put a FPGA in a SBus system (SPARCstation) https://github.com/rdolbeau/SBusFPGA 0 comments
- LiteX on the SQRL Acorn FPGA – Tea and Tech Time https://teaandtechtime.com/litex-on-the-sqrl-acorn-fpga/ 0 comments
- Bluespec. The Rust of Hardware Design? - Thoughts From a Programmer https://yehowshuaimmanuel.com/posts/bluespec-the-rust-of-hardware/ 0 comments
Linked pages
- Homebrew — The Missing Package Manager for macOS (or Linux) https://brew.sh 184 comments
- Use LiteX on the Acorn CLE 215 · enjoy-digital/litex Wiki · GitHub https://github.com/enjoy-digital/litex/wiki/Use-LiteX-on-the-Acorn-CLE-215 0 comments
- LiteX vs. Vivado: First Impressions « bunnie's blog https://www.bunniestudios.com/blog/?p=5018 0 comments
- GitHub - m-labs/migen: A Python toolbox for building complex digital hardware https://github.com/m-labs/migen 0 comments
- GitHub - litex-hub/linux-on-litex-vexriscv: Linux on LiteX-VexRiscv https://github.com/litex-hub/linux-on-litex-vexriscv 0 comments
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