- Looking for a RISC-V single board computer with Open Source RISC-V implementation https://github.com/suryakantamangaraj/AwesomeRISC-VResources?tab=readme-ov-file#cores 8 comments riscv
Linked pages
- Creative Commons — CC0 1.0 Universal http://creativecommons.org/publicdomain/zero/1.0/ 305 comments
- RISC-V Offers Simple, Modular ISA - RISC-V International http://riscv.org/2016/04/risc-v-offers-simple-modular-isa/ 197 comments
- GitHub - darklife/darkriscv: opensouce RISC-V cpu core implemented in Verilog from scratch in one night! https://github.com/darklife/darkriscv 161 comments
- BOOM v2: an open-source out-of-order RISC-V core | EECS at UC Berkeley https://www2.eecs.berkeley.edu/pubs/techrpts/2017/eecs-2017-157.html 107 comments
- GitHub - rsd-devel/rsd: RSD: RISC-V Out-of-Order Superscalar Processor https://github.com/rsd-devel/rsd 83 comments
- GitHub - openhwgroup/cva6: The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux https://github.com/openhwgroup/cva6 71 comments
- GitHub - riscv-collab/riscv-gnu-toolchain: GNU toolchain for RISC-V, including GCC https://github.com/riscv/riscv-gnu-toolchain 62 comments
- GitHub - mrLSD/riscv-fs: F# RISC-V Instruction Set formal specification https://github.com/mrLSD/riscv-fs 61 comments
- GitHub - chipsalliance/Cores-VeeR-EH1: VeeR EH1 core https://github.com/chipsalliance/Cores-SweRV 59 comments
- [1906.00478] Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI https://arxiv.org/abs/1906.00478 56 comments
- TinyEMU https://bellard.org/tinyemu/ 46 comments
- GitHub - openhwgroup/cva6: The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux https://github.com/pulp-platform/ariane 43 comments
- GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation https://github.com/SpinalHDL/VexRiscv 43 comments
- Chisel/FIRRTL: Home https://www.chisel-lang.org/ 39 comments
- GitHub - TheThirdOne/rars: RARS -- RISC-V Assembler and Runtime Simulator https://github.com/TheThirdOne/rars 30 comments
- GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. https://github.com/stnolting/neorv32 29 comments
- RISC-V Bases and Extensions Explained - CNX Software https://www.cnx-software.com/2019/08/27/risc-v-bases-and-extensions-explained/ 27 comments
- GitHub - sifive/freedom: Source files for SiFive's Freedom platforms https://github.com/sifive/freedom 21 comments
- GitHub - mortbopet/Ripes: A graphical processor simulator and assembly editor for the RISC-V ISA https://github.com/mortbopet/Ripes 16 comments
- GitHub - ultraembedded/biriscv: 32-bit Superscalar RISC-V CPU https://github.com/ultraembedded/biriscv 15 comments
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