Hacker News
- RISC-V needs some love! The first open source instruction set to be (at least somewhat) widely adopted! https://riscv.org/ 11 comments opensource
- RISC-V is a new instruction set architecture designed to support computer architecture research and education. http://riscv.org/ 22 comments programming
Linking pages
- Stop future proofing software. You can read this article on my own… | by George Hosu | Medium https://medium.com/@george3d6/stop-future-proofing-software-c984cbd65e78 336 comments
- Google, HP, Oracle Join RISC-V - EE Times http://www.eetimes.com/document.asp?amp%3B=&doc_id=1328561 236 comments
- Wait, What? MIPS Becomes RISC-V – EEJournal https://www.eejournal.com/article/wait-what-mips-becomes-risc-v/ 222 comments
- India's First CPUs Are Ready for App Development | Tom's Hardware https://www.tomshardware.com/news/india-shakti-cpu-processors-sdk-risc-v,39781.html 194 comments
- Nvidia’s Integration Dreams – Stratechery by Ben Thompson https://stratechery.com/2020/nvidias-integration-dreams/ 189 comments
- Google, HP, Oracle Join RISC-V - EE Times http://www.eetimes.com/document.asp?doc_id=1328561 157 comments
- RISC-V on the Verge of Broad Adoption - EE Times https://www.eetimes.com/document.asp?doc_id=1334311 139 comments
- RISC creator is pushing open source chips for cloud computing and the internet of things – Old GigaOm http://gigaom.com/2014/08/19/risc-creator-is-pushing-open-source-chips-for-cloud-computing-and-the-internet-of-things/ 113 comments
- RISC-V only takes 12 years to achieve the milestone of 10 billion cores https://www.cosfone.com/risc-v-only-takes-12-years-to-achieve-the-milestone-of-10-billion-cores/ 102 comments
- GitHub - standardsemiconductor/lion: Where Lions Roam: RISC-V on the VELDT https://github.com/standardsemiconductor/lion 99 comments
- First RISC: John Cocke and the IBM 801 - by Babbage https://thechipletter.substack.com/p/the-first-risc-john-cocke-and-the 89 comments
- Manuel A. Fernandez Montecelo :: Personal Debian page -- Debian GNU/Linux port for RISC-V 64-bit (riscv64) https://people.debian.org/~mafm/posts/2017/20170422_debian-gnulinux-port-for-risc-v-64-bit-riscv64/ 81 comments
- RISC-V International Reports Another Strong Year of Growth with New Technical Milestones, Educational Programs, RISC-V Adoption and More https://www.hpcwire.com/off-the-wire/risc-v-international-reports-another-strong-year-of-growth-with-new-technical-milestones-educational-programs-risc-v-adoption-and-more/ 65 comments
- GitHub - levskaya/jslinux-deobfuscated: An old version of Mr. Bellard's JSLinux rewritten to be human readable, hand deobfuscated and annotated. https://github.com/levskaya/jslinux-deobfuscated 60 comments
- GitHub - Ly0n/awesome-robotic-tooling: Tooling for professional robotic development in C++ and Python with a touch of ROS, autonomous driving and aerospace https://github.com/Ly0n/awesome-robotic-tooling 54 comments
- First Linux-Based RISC-V Board Prepares for Take-Off - Linux.com https://www.linux.com/blog/event/elc-open-iot/2018/2/first-linux-based-risc-v-board-prepares-take 52 comments
- Open Source Core Advances - EE Times http://www.eetimes.com/author.asp?doc_id=1327129§ion_id=36 38 comments
- BSC Working Towards First Completely Open Source European Full-Stack Ecosystem Based on New RISC-V CPU https://www.hpcwire.com/off-the-wire/bsc-working-towards-first-completely-open-source-european-full-stack-ecosystem-based-on-new-risc-v-cpu/ 37 comments
- GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. https://github.com/stnolting/neorv32 29 comments
- Why open hardware needs open software – and more from Wayne Stambaugh of KiCad – SnapEDA Blog http://blog.snapeda.com/2019/10/28/an-interview-with-wayne-stambaugh-of-kicad/ 29 comments
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