Hacker News
- NEORV32: A tiny, embedded and free-of-charge open-source RISC-V SoC https://github.com/stnolting/neorv32/blob/main/README.md 6 comments
Linked pages
- RISC-V International https://riscv.org/ 52 comments
- GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. https://github.com/stnolting/neorv32 29 comments
- GitHub - stnolting/neoTRNG: 🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC). https://github.com/stnolting/neoTRNG 4 comments
- GitHub - enjoy-digital/litex: Build your hardware, easily! https://github.com/enjoy-digital/litex 3 comments
- GitHub - stnolting/neorv32-verilog: ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL. https://github.com/stnolting/neorv32-verilog 0 comments
- GitHub - stnolting/neorv32-riscof: ✔️ Verify the NEORV32 Processor's RISC-V compatibility using RISCOF. https://github.com/stnolting/neorv32-riscof 0 comments
- [Datasheet] The NEORV32 RISC-V Processor https://stnolting.github.io/neorv32/ 0 comments
- NEORV32 — Zephyr Project Documentation https://docs.zephyrproject.org/latest/boards/riscv/neorv32/doc/index.html 0 comments
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