- Looking for a RISC-V core for verification https://github.com/riscvarchive/riscv-cores-list 11 comments riscv
Linked pages
- HiFive Unleashed (Discontinued) - SiFive https://www.sifive.com/products/hifive-unleashed/ 357 comments
- GitHub - darklife/darkriscv: opensouce RISC-V cpu core implemented in Verilog from scratch in one night! https://github.com/darklife/darkriscv 161 comments
- Shakti Processor | Home http://shakti.org.in/ 93 comments
- GitHub - rsd-devel/rsd: RSD: RISC-V Out-of-Order Superscalar Processor https://github.com/rsd-devel/rsd 83 comments
- GitHub - openhwgroup/cva6: The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux https://github.com/openhwgroup/cva6 71 comments
- PULP FAQs http://www.pulp-platform.org/ 61 comments
- GitHub - chipsalliance/Cores-VeeR-EH1: VeeR EH1 core https://github.com/chipsalliance/Cores-SweRV 59 comments
- GitHub - openhwgroup/cva6: The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux https://github.com/pulp-platform/ariane 43 comments
- GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation https://github.com/SpinalHDL/VexRiscv 43 comments
- GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. https://github.com/stnolting/neorv32 29 comments
- GitHub - sifive/freedom: Source files for SiFive's Freedom platforms https://github.com/sifive/freedom 21 comments
- HiFive1 Rev B - SiFive https://www.sifive.com/boards/hifive1-rev-b 20 comments
- RISC-V BOOM - RISC-V BOOM https://boom-core.org/ 18 comments
- GitHub - ultraembedded/biriscv: 32-bit Superscalar RISC-V CPU https://github.com/ultraembedded/biriscv 15 comments
- FireSim https://fires.im/ 11 comments
- http://parallel.princeton.edu/openpiton/ 10 comments
- GitHub - olofk/serv: SERV - The SErial RISC-V CPU https://github.com/olofk/serv 6 comments
- GitHub - lcbcFoo/ReonV: ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA. https://github.com/lcbcFoo/ReonV 5 comments
- GitHub - enjoy-digital/litex: Build your hardware, easily! https://github.com/enjoy-digital/litex 3 comments
- GitHub - lowRISC/ibex: Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. https://github.com/lowRISC/ibex 2 comments
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