Hacker News
- VexRiscv is a quadcore, Linux-capable RISC-V softcore for FPGA https://antmicro.com/blog/2020/05/multicore-vex-in-litex/ 77 comments
Linked pages
- GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation https://github.com/SpinalHDL/VexRiscv 43 comments
- GitHub - verilator/verilator: Verilator open-source SystemVerilog simulator and lint system https://github.com/verilator/verilator 7 comments
- GitHub - enjoy-digital/litex: Build your hardware, easily! https://github.com/enjoy-digital/litex 3 comments
- GitHub - m-labs/migen: A Python toolbox for building complex digital hardware https://github.com/m-labs/migen 0 comments
Related searches:
Search whole site: site:antmicro.com
Search title: Antmicro · Running Linux with Quad-core SMP in LiteX/VexRiscv on Arty A7
See how to search.