Hacker News
Lobsters
Linking pages
- New CoreScore World Record Crams 6,000 SERV RISC-V Cores Into a Single FPGA - Hackster.io https://www.hackster.io/news/new-corescore-world-record-crams-6-000-serv-risc-v-cores-into-a-single-fpga-2fc6022247e0 12 comments
- GitHub - riscvarchive/riscv-cores-list: RISC-V Cores, SoC platforms and SoCs https://github.com/riscvarchive/riscv-cores-list 11 comments
- GitHub - suryakantamangaraj/AwesomeRISC-VResources: It contains a curated list of awesome RISC-V Resources. https://github.com/suryakantamangaraj/AwesomeRISC-VResources?tab=readme-ov-file#cores 8 comments
- GitHub - riscvarchive/riscv-cores-list: RISC-V Cores, SoC platforms and SoCs https://github.com/riscv/riscv-cores-list 0 comments
- GDBWave - A Post-Simulation Waveform-Based RISC-V GDB Debugging Server | Electronics etc… https://tomverbeure.github.io/2022/02/20/GDBWave-Post-Simulation-RISCV-SW-Debugging.html 0 comments
- GitHub - aolofsson/awesome-opensource-hardware: List of awesome open source hardware tools, generators, and reusable designs https://github.com/aolofsson/awesome-opensource-hardware 0 comments
Linked pages
- Zephyr Project - Zephyr Project https://www.zephyrproject.org/ 119 comments
- GitHub - riscv-collab/riscv-gnu-toolchain: GNU toolchain for RISC-V, including GCC https://github.com/riscv-collab/riscv-gnu-toolchain 41 comments
- Veripool https://www.veripool.org/wiki/verilator 19 comments
- GitHub - enjoy-digital/litex: Build your hardware, easily! https://github.com/enjoy-digital/litex 3 comments
- Bit by bit - How to fit 8 RISC V cores in a $38 FPGA board - YouTube https://www.youtube.com/watch?v=xjIxORBRaeQ 0 comments
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