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- Antmicro · Running Linux with Quad-core SMP in LiteX/VexRiscv on Arty A7 https://antmicro.com/blog/2020/05/multicore-vex-in-litex/ 77 comments
- FPGA: Why so few open source drivers for open hardware? - mupuf.org https://mupuf.org/blog/2020/06/09/FPGA-why-so-few-drivers/ 24 comments
- A Pixel Purse LED Cube Controlled by a Cisco 3G Modem | Electronics etc… https://tomverbeure.github.io/2021/05/16/Pixel-Purse-LED-Cube.html 18 comments
- GitHub - riscvarchive/riscv-cores-list: RISC-V Cores, SoC platforms and SoCs https://github.com/riscvarchive/riscv-cores-list 11 comments
- GitHub - suryakantamangaraj/AwesomeRISC-VResources: It contains a curated list of awesome RISC-V Resources. https://github.com/suryakantamangaraj/AwesomeRISC-VResources?tab=readme-ov-file#cores 8 comments
- Rust on Risc-V (VexRiscv) on SpinalHDL with SymbiFlow on the Hackaday Supercon Badge · Craig J. Bishop https://craigjb.com/2020/01/22/ecp5/ 6 comments
- GitHub - google/CFU-Playground: Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below. https://github.com/google/CFU-Playground 4 comments
- Semihosting, your PC as Console of an Embedded RISC-V CPU | Electronics etc… https://tomverbeure.github.io/2021/12/30/Semihosting-on-RISCV.html 0 comments
- GitHub - riscvarchive/riscv-cores-list: RISC-V Cores, SoC platforms and SoCs https://github.com/riscv/riscv-cores-list 0 comments
- Getting Started with ECP5 FPGAs on the Colorlight i5 FPGA Development Board | Electronics etc… https://tomverbeure.github.io/2021/01/22/The-Colorlight-i5-as-FPGA-development-board.html 0 comments
- VexRiscv, OpenOCD, and Traps | Electronics etc… https://tomverbeure.github.io/2021/07/18/VexRiscv-OpenOCD-and-Traps.html 0 comments
- GitHub - madushan1000/freedom-phone: Completely free(as in freedom) phone/handheld device https://github.com/madushan1000/freedom-phone 0 comments
- GDBWave - A Post-Simulation Waveform-Based RISC-V GDB Debugging Server | Electronics etc… https://tomverbeure.github.io/2022/02/20/GDBWave-Post-Simulation-RISCV-SW-Debugging.html 0 comments
- The VexRiscV CPU - A New Way to Design | Electronics etc… https://tomverbeure.github.io/rtl/2018/12/06/The-VexRiscV-CPU-A-New-Way-To-Design.html 0 comments
- GitHub - m-labs/artiq: A leading-edge control system for quantum information experiments https://github.com/m-labs/artiq 0 comments
- GitHub - litex-hub/linux-on-litex-vexriscv: Linux on LiteX-VexRiscv https://github.com/litex-hub/linux-on-litex-vexriscv 0 comments
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