GitHub - SpinalHDL/openocd_riscv: Spen's Official OpenOCD Mirror - discu.eu

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How can I debug risc-v on an FPGA board https://github.com/SpinalHDL/openocd_riscv 2 comments 13/1/2021 riscv

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GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation https://github.com/SpinalHDL/VexRiscv 43 comments
VexRiscv, OpenOCD, and Traps | Electronics etc… https://tomverbeure.github.io/2021/07/18/VexRiscv-OpenOCD-and-Traps.html 0 comments

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