Linking pages
- GitHub - Forty-Bot/ethernet: WIP 100BASE-TX PHY https://github.com/Forty-Bot/ethernet 65 comments
- GitHub - aolofsson/awesome-hardware-tools: List of awesome open source hardware tools https://github.com/aolofsson/awesome-hardware-tools 36 comments
- GitHub - GlasgowEmbedded/glasgow: Scots Army Knife for electronics https://github.com/GlasgowEmbedded/glasgow 27 comments
- GitHub - ghdl/ghdl-yosys-plugin: VHDL synthesis (based on ghdl) https://github.com/ghdl/ghdl-yosys-plugin 14 comments
- GitHub - vmware-archive/cascade: A Just-In-Time Compiler for Verilog from VMware Research https://github.com/vmware/cascade 13 comments
- FPGA vendor Lattice acknowledges value of open source community – Open Source Specialist Group https://ossg.bcs.org/blog/2020/06/28/fpga-vendor-lattice-acknowledges-value-of-open-source-community/ 9 comments
- GitHub - suryakantamangaraj/AwesomeRISC-VResources: It contains a curated list of awesome RISC-V Resources. https://github.com/suryakantamangaraj/AwesomeRISC-VResources?tab=readme-ov-file#cores 8 comments
- Rust on Risc-V (VexRiscv) on SpinalHDL with SymbiFlow on the Hackaday Supercon Badge · Craig J. Bishop https://craigjb.com/2020/01/22/ecp5/ 6 comments
- Throwing Verilog Users a Bone with an Open Source FPGA Dev Board - Hackster.io https://www.hackster.io/news/throwing-verilog-users-a-bone-with-an-open-source-fpga-dev-board-b5557d388187 6 comments
- ROT256 : Cryptography & Other Random Bits. https://rot256.io/post/glitch/ 5 comments
- spispy: Open source flash emulation - Trammell Hudson's Projects https://trmm.net/Spispy 1 comment
- GitHub - YosysHQ/apicula: Project Apicula 🐝: bitstream documentation for Gowin FPGAs https://github.com/YosysHQ/apicula 1 comment
- Logic Primitive Transformations with Yosys Techmap | Electronics etc… https://tomverbeure.github.io/2022/11/18/Primitive-Transformations-with-Yosys-Techmap.html 1 comment
- GitHub - YosysHQ/prjtrellis: Documenting the Lattice ECP5 bit-stream format. https://github.com/YosysHQ/prjtrellis 0 comments
- Sipeed Tang Nano FPGA and Open Source toolchain – GeekLAN https://www.geeklan.co.uk/?p=2919 0 comments
- GitHub - oxidecomputer/cobalt: A collection of common Bluespec interfaces/modules. https://github.com/oxidecomputer/cobalt 0 comments
- Getting Started with ECP5 FPGAs on the Colorlight i5 FPGA Development Board | Electronics etc… https://tomverbeure.github.io/2021/01/22/The-Colorlight-i5-as-FPGA-development-board.html 0 comments
- Lattice et l'open-source, la fin d'un rêve ? - LinuxFr.org https://linuxfr.org/users/martoni/journaux/lattice-et-l-open-source-la-fin-d-un-reve 0 comments
- GitHub - YosysHQ/arachne-pnr: Place and route tool for FPGAs https://github.com/cseed/arachne-pnr 0 comments
- firmware-anatomy/hw_security.md at master · hardenedlinux/firmware-anatomy · GitHub https://github.com/hardenedlinux/firmware-anatomy/blob/master/hack_ME/hw_security.md 0 comments
Linked pages
- Verilog to Routing https://verilogtorouting.org/ 29 comments
- Python Release Python 3.6.4 | Python.org https://www.python.org/downloads/release/python-364/ 3 comments
- GitHub - YosysHQ/apicula: Project Apicula 🐝: bitstream documentation for Gowin FPGAs https://github.com/YosysHQ/apicula 1 comment
- GitHub - YosysHQ/prjtrellis: Documenting the Lattice ECP5 bit-stream format. https://github.com/YosysHQ/prjtrellis 0 comments
- [1903.10407] Yosys+nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs https://arxiv.org/abs/1903.10407 0 comments
- GitHub - YosysHQ/arachne-pnr: Place and route tool for FPGAs https://github.com/cseed/arachne-pnr 0 comments
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