Hacker News
- VHDL support for open-source FPGA toolchain YoSys https://github.com/ghdl/ghdl-yosys-plugin 14 comments
Linking pages
- GitHub - Redcrafter/verilog2factorio: This project will compile verilog (a hardware description language) into factorio blueprints. https://github.com/Redcrafter/verilog2factorio/ 98 comments
- CXXRTL, a Yosys Simulation Backend | Electronics etc… https://tomverbeure.github.io/2020/08/08/CXXRTL-the-New-Yosys-Simulation-Backend.html 2 comments
- arl/README-VHDL.md at master · kaxap/arl · GitHub https://github.com/kaxap/arl/blob/master/README-VHDL.md 2 comments
Linked pages
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