Hacker News
- FuseSoC – Package manager and build abstraction tool for FPGA/ASIC development https://github.com/olofk/fusesoc 2 comments
Linking pages
- GitHub - Ly0n/awesome-robotic-tooling: Tooling for professional robotic development in C++ and Python with a touch of ROS, autonomous driving and aerospace https://github.com/Ly0n/awesome-robotic-tooling 54 comments
- GitHub - aolofsson/awesome-hardware-tools: List of awesome open source hardware tools https://github.com/aolofsson/awesome-hardware-tools 36 comments
- Electronics | Free Full-Text | Embedded LUKS (E-LUKS): A Hardware Solution to IoT Security https://www.mdpi.com/2079-9292/10/23/3036 11 comments
- GitHub - mikeroyal/RISC-V-Guide: RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware. https://github.com/mikeroyal/RISC-V-Guide 10 comments
- GitHub - suryakantamangaraj/AwesomeRISC-VResources: It contains a curated list of awesome RISC-V Resources. https://github.com/suryakantamangaraj/AwesomeRISC-VResources?tab=readme-ov-file#cores 8 comments
- Building an FPGA Game Boy emulator | Eli Lipsitz https://eli.lipsitz.net/posts/fpga-gameboy-emulator/ 6 comments
- GitHub - secworks/sha256: Hardware implementation of the SHA-256 cryptographic hash function https://github.com/secworks/sha256 3 comments
- GitHub - mikeroyal/VHDL-Guide: VHDL Guide https://github.com/mikeroyal/VHDL-Guide 2 comments
- GitHub - carlosedp/chisel-fpga-pinfinder: A Chisel implementation for an FPGA Pin Finder thru UART https://github.com/carlosedp/chisel-fpga-pinfinder 1 comment
- GitHub - craigjb/fuse-zynq: Generate Zynq configurations without using the vendor GUI https://github.com/craigjb/fuse-zynq 0 comments
- GitHub - protontypes/awesome-robotic-tooling: Tooling for professional robotic development in C++ and Python with a touch of ROS, autonomous driving and aerospace. https://github.com/protontypes/awesome-robotic-tooling 0 comments
- GitHub - secworks/prince: The Prince lightweight block cipher in Verilog. https://github.com/secworks/prince 0 comments
- GitHub - benreynwar/pyvivado: Python tools for Vivado Projects https://github.com/benreynwar/pyvivado 0 comments
- GitHub - aolofsson/oh: Verilog library for ASIC and FPGA designers https://github.com/parallella/oh 0 comments
- GitHub - aolofsson/awesome-opensource-hardware: List of awesome open source hardware tools, generators, and reusable designs https://github.com/aolofsson/awesome-opensource-hardware 0 comments
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