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Linking pages
- FPGA Design for Software Engineers, Part 1 - Verilog and State Machines // Walk N' Squalk Coding Blog https://www.walknsqualk.com/post/014-tiny-fpga-bx/ 108 comments
- GitHub - jbush001/NyuziProcessor: GPGPU microprocessor architecture https://github.com/jbush001/NyuziProcessor 99 comments
- Clocks for Software Engineers https://zipcpu.com/blog/2017/09/18/clocks-for-sw-engineers.html 62 comments
- Inside Tesla’s Neural Processor In The FSD Chip – WikiChip Fuse https://fuse.wikichip.org/news/2707/inside-teslas-neural-processor-in-the-fsd-chip/ 53 comments
- GitHub - kitspace/awesome-electronics: A curated list of awesome resources for electronic engineers and hobbyists https://github.com/monostable/awesome-electronics 51 comments
- About the ZipCPU http://zipcpu.com/about/zipcpu.html 46 comments
- GitHub - jbush001/NyuziProcessor: GPGPU microprocessor architecture https://github.com/jbush001/GPGPU 29 comments
- GitHub - vmware-archive/cascade: A Just-In-Time Compiler for Verilog from VMware Research https://github.com/vmware/cascade 13 comments
- GitHub - olofk/serv: SERV - The SErial RISC-V CPU https://github.com/olofk/serv 6 comments
- GitHub - atgreen/wrapilator: Wraps verilator output in Common Lisp for testing digital logic in Lisp http://github.com/atgreen/wrapilator 5 comments
- GitHub - secworks/sha256: Hardware implementation of the SHA-256 cryptographic hash function https://github.com/secworks/sha256 3 comments
- CXXRTL, a Yosys Simulation Backend | Electronics etc… https://tomverbeure.github.io/2020/08/08/CXXRTL-the-New-Yosys-Simulation-Backend.html 2 comments
- Verilog, Formal Verification and Verilator Beginner's Tutorial https://zipcpu.com/tutorial/ 1 comment
- GitHub - tilk/riscv-simple-sv: A simple RISC V core for teaching https://github.com/tilk/riscv-simple-sv 1 comment
- Using a CORDIC to calculate sines and cosines in an FPGA http://zipcpu.com/dsp/2017/08/30/cordic.html 0 comments
- GitHub - tymonx/logic: CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs. https://github.com/tymonx/logic 0 comments
- A dive into RI5CY core internals – Embecosm https://www.embecosm.com/2019/08/13/a-dive-into-ri5cy-core-internals/ 0 comments
- GitHub - FPGAwars/apio: Open source ecosystem for open FPGA boards https://github.com/FPGAwars/apio 0 comments
- Use FPGA Open Source Toolchain with Private Island and Lattice ECP5UM https://mindchasers.com/dev/tools-fpga-open-source 0 comments
- GitHub - aolofsson/oh: Verilog library for ASIC and FPGA designers https://github.com/parallella/oh 0 comments