Linking pages
- Google’s Fully Homomorphic Encryption Compiler — A Primer – Math ∩ Programming https://jeremykun.com/2023/02/13/googles-fully-homomorphic-encryption-compiler-a-primer/ 260 comments
- GitHub - zeroasiccorp/logik: A configurable RTL to bitstream FPGA toolchain https://github.com/zeroasiccorp/logik 35 comments
- GitHub - tilk/digitaljs: Teaching-focused digital circuit simulator https://github.com/tilk/digitaljs 27 comments
- GitHub - gatecat/prjoxide: Documenting Lattice's 28nm FPGA parts https://github.com/daveshah1/prjoxide 23 comments
- GitHub - ghdl/ghdl-yosys-plugin: VHDL synthesis (based on ghdl) https://github.com/ghdl/ghdl-yosys-plugin 14 comments
- Calculating Actual Build Dependencies – Ian McKellar https://ianloic.com/2019/09/13/strace-deps/ 6 comments
- embedded-iot_profile/opentitan-rtl-synthesis-with-yosys.md at master · hardenedlinux/embedded-iot_profile · GitHub https://github.com/hardenedlinux/embedded-iot_profile/blob/master/docs/opentitan/opentitan-rtl-synthesis-with-yosys.md 6 comments
- Hardware Trojans Under a Microscope | by Ryan Cornateanu | Medium https://ryancor.medium.com/hardware-trojans-under-a-microscope-bf542acbcc29 6 comments
- Antmicro · Accelerating digital block design with Googleâs open source Mid-Level Synthesis XLS toolchain https://antmicro.com/blog/2023/09/accelerating-digital-block-design-with-googles-xls/ 2 comments
- GateMate FPGA – Cologne Chip https://www.colognechip.com/programmable-logic/gatemate/ 1 comment
- GitHub - chipsalliance/firrtl: Flexible Intermediate Representation for RTL https://github.com/chipsalliance/firrtl 1 comment
- GitHub - YosysHQ/prjtrellis: Documenting the Lattice ECP5 bit-stream format. https://github.com/YosysHQ/prjtrellis 0 comments
- Sipeed Tang Nano FPGA and Open Source toolchain – GeekLAN https://www.geeklan.co.uk/?p=2919 0 comments
- GitHub - oxidecomputer/cobalt: A collection of common Bluespec interfaces/modules. https://github.com/oxidecomputer/cobalt 0 comments
- Getting Started with ECP5 FPGAs on the Colorlight i5 FPGA Development Board | Electronics etc… https://tomverbeure.github.io/2021/01/22/The-Colorlight-i5-as-FPGA-development-board.html 0 comments
- firmware-anatomy/hw_security.md at master · hardenedlinux/firmware-anatomy · GitHub https://github.com/hardenedlinux/firmware-anatomy/blob/master/hack_ME/hw_security.md 0 comments
- How to Build a Trustworthy Free/Libre Linux Capable 64-bit RISC-V Computer https://insights.sei.cmu.edu/sei_blog/2019/10/how-to-build-a-trustworthy-freelibre-linux-capable-64-bit-risc-v-computer.html 0 comments
- GitHub - vmunoz82/eda_tools: A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator. https://github.com/vmunoz82/eda_tools 0 comments
- GitHub - YosysHQ/apicula: Project Apicula 🐝: bitstream documentation for Gowin FPGAs https://github.com/pepijndevos/apicula/ 0 comments
- Logic Primitive Transformations with Yosys Techmap https://blog.yosyshq.com/p/logic-primitive-transformations-with-yosys-techmap/ 0 comments
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