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- GitHub - analysis-tools-dev/static-analysis: ⚙️ A curated list of static analysis (SAST) tools and linters for all programming languages, config files, build tools, and more. The focus is on tools which improve code quality. https://github.com/analysis-tools-dev/static-analysis 112 comments
- XLS: Accelerated HW Synthesis https://google.github.io/xls/ 67 comments
- GitHub - analysis-tools-dev/static-analysis: ⚙️ A curated list of static analysis (SAST) tools and linters for all programming languages, config files, build tools, and more. The focus is on tools which improve code quality. https://github.com/mre/awesome-static-analysis#c 21 comments
- GitHub - Fraunhofer-IMS/airisc_core_complex: Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional periperals. https://github.com/Fraunhofer-IMS/airisc_core_complex 5 comments
- GitHub - GiulioCocconi/verigoodtest https://github.com/GiulioCocconi/verigoodtest 1 comment
- GitHub - stnolting/neorv32-verilog: ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL. https://github.com/stnolting/neorv32-verilog 0 comments
- GDBWave - A Post-Simulation Waveform-Based RISC-V GDB Debugging Server | Electronics etc… https://tomverbeure.github.io/2022/02/20/GDBWave-Post-Simulation-RISCV-SW-Debugging.html 0 comments
- GitHub - mohamed/fsm2sv: SystemVerilog FSM generator https://github.com/mohamed/fsm2sv 0 comments
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