Hacker News
- Intel unveils BonanzaMine, a Bitcoin accelerator ASIC https://fuse.wikichip.org/news/6603/intel-unveils-bonanzamine-a-bitcoin-accelerator-asic/ 129 comments
- Arm Updates Its Neoverse Roadmap: New BFloat16, SVE Support https://fuse.wikichip.org/news/4564/arm-updates-its-neoverse-roadmap-new-bfloat16-sve-support/ 13 comments
- Esperanto exits stealth mode, aims at AI with a 4,096-core 7nm RISC-V monster https://fuse.wikichip.org/news/686/esperanto-exits-stealth-mode-aims-at-ai-with-a-4096-core-7nm-risc-v-monster/ 8 comments
- IEDM 2017: AMD’s grand vision for the future of HPC – WikiChip Fuse https://fuse.wikichip.org/news/523/iedm-2017-amds-grand-vision-for-the-future-of-hpc/ 3 comments
- Chiplets for RISC-V https://fuse.wikichip.org/news/3199/ocp-bunch-of-wires-a-new-open-chiplets-interface-for-organic-substrates/ 15 comments riscv
- A Look At The ET-SoC-1, Esperanto's Massively Multi-Core RISC-V Approach To AI https://fuse.wikichip.org/news/4911/a-look-at-the-et-soc-1-esperantos-massively-multi-core-risc-v-approach-to-ai/ 6 comments riscv
- AMD 3D Stacks SRAM Bumplessly https://fuse.wikichip.org/news/5531/amd-3d-stacks-sram-bumplessly/ 6 comments technology
- AMD 3D Stacks SRAM Bumplessly https://fuse.wikichip.org/news/5531/amd-3d-stacks-sram-bumplessly/ 35 comments hardware
- A Look At The ET-SoC-1, Esperanto's Massively Multi-Core RISC-V Approach To AI https://fuse.wikichip.org/news/4911/a-look-at-the-et-soc-1-esperantos-massively-multi-core-risc-v-approach-to-ai/ 9 comments riscv
- Arm updates its Neoverse roadmap, with bfloat16 and SVE support for the Zeus platform https://fuse.wikichip.org/news/4564/arm-updates-its-neoverse-roadmap-new-bfloat16-sve-support/ 33 comments hardware
- The x86 Advanced Matrix Extension (AMX) Brings Matrix Operations https://fuse.wikichip.org/news/3600/the-x86-advanced-matrix-extension-amx-brings-matrix-operations-to-debut-with-sapphire-rapids/ 3 comments asm
- Arm’s New Cortex-M55 Breathes Helium https://fuse.wikichip.org/news/3319/arms-new-cortex-m55-breathes-helium/ 9 comments hardware
- TSMC Details 5 nm https://fuse.wikichip.org/news/3398/tsmc-details-5-nm/ 52 comments hardware
- A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC https://fuse.wikichip.org/news/3217/a-look-at-celeritys-second-gen-496-core-risc-v-mesh-noc/ 3 comments hardware
- TSMC leverages existing silicon in the CoWoS process to improve the power delivery system of high-performance applications through new, deep trench capacitors, codename iCAPs. https://fuse.wikichip.org/news/3144/tsmc-digs-trenches-in-search-of-higher-performance/ 4 comments hardware
- Groq Tensor Streaming Processor Delivers 1 PetaOPS of Compute https://fuse.wikichip.org/news/3005/groq-tensor-streaming-processor-delivers-1-petaops-of-compute/ 13 comments hardware
- DARPA ERI: HIVE and Intel PUMA Graph Processor - WikiChip https://fuse.wikichip.org/news/2611/darpa-eri-hive-and-intel-puma-graph-processor/ 7 comments hardware
- SEMICON West 2019: ASML EUV Update – WikiChip Fuse https://fuse.wikichip.org/news/2550/semicon-west-2019-asml-euv-update/ 4 comments hardware
- Intel Introduces Co-EMIB To Stitch Multiple 3D Die Stacks Together, Adds Omni-Directional Interconnects https://fuse.wikichip.org/news/2503/intel-introduces-co-emib-to-stitch-multiple-3d-die-stacks-together-adds-omni-directional-interconnects/ 39 comments hardware
- Intel Sunny Cove Core To Deliver A Major Improvement In Single-Thread Performance, Bigger Improvements To Follow https://fuse.wikichip.org/news/2371/intel-sunny-cove-core-to-deliver-a-major-improvement-in-single-thread-performance-bigger-improvements-to-follow/ 270 comments hardware
- Intel Process Technology And Packaging Plans: 10nm in June, 7nm in 2021 https://fuse.wikichip.org/news/2293/intel-process-technology-and-packaging-plans-10nm-in-june-7nm-in-2021/ 76 comments hardware
- Samsung Discloses Exynos M4 Changes, Upgrades Support for ARMv8.2, Rearranges The Back-End https://fuse.wikichip.org/news/2051/samsung-discloses-exynos-m4-changes-upgrades-support-for-armv8-2-rearranges-the-back-end/ 6 comments hardware
- Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips - WikiChip https://fuse.wikichip.org/news/1941/intel-reveals-10nm-sunny-cove-core-a-new-core-roadmap-and-teases-ice-lake-chips/ 43 comments intel
- Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes - WikiChip https://fuse.wikichip.org/news/1910/intel-looks-to-advanced-3d-packaging-for-more-than-moore-to-supplement-10-and-7-nanometer-nodes/ 12 comments intel
- Intel Reveals 10nm Sunny Cove Core, a New Core Roadmap, and Teases Ice Lake Chips - WikiChip https://fuse.wikichip.org/news/1941/intel-reveals-10nm-sunny-cove-core-a-new-core-roadmap-and-teases-ice-lake-chips/ 127 comments hardware
- Intel Looks to Advanced 3D Packaging For More-than-Moore to Supplement 10- and 7-Nanometer Nodes – WikiChip Fuse https://fuse.wikichip.org/news/1910/intel-looks-to-advanced-3d-packaging-for-more-than-moore-to-supplement-10-and-7-nanometer-nodes/ 47 comments hardware
- A Look at NEC’s Latest Vector Processor, the SX-Aurora https://fuse.wikichip.org/news/1833/a-look-at-necs-latest-vector-processor-the-sx-aurora/ 9 comments hardware
- SiFive Launches 7 Series, Their Highest Performance RISC-V Cores – WikiChip Fuse https://fuse.wikichip.org/news/1775/sifive-launches-7-series-their-highest-performance-risc-v-cores/ 4 comments hardware
- AMD Announces Threadripper 2, Chiplets Aid Core Scaling https://fuse.wikichip.org/news/1569/amd-announces-threadripper-2-chiplets-aid-core-scaling/ 53 comments hardware
- Intel Opens AIB for DARPA’s CHIPS Program as a Royalty-Free Interconnect Standard for Chiplet Architectures https://fuse.wikichip.org/news/1520/intel-opens-aib-for-darpas-chips-program-as-a-royalty-free-interconnect-standard-for-chiplet-architectures/ 16 comments hardware
- Cambricon Reaches for the Cloud With a Custom AI Accelerator, Talks 7nm IPs https://fuse.wikichip.org/news/1297/cambricon-reaches-for-the-cloud-with-a-custom-ai-accelerator-talks-7nm-ips/ 19 comments hardware
- A look at Nvidia’s NVLink interconnect and the NVSwitch - WikiChip https://fuse.wikichip.org/news/1224/a-look-at-nvidias-nvlink-interconnect-and-the-nvswitch/ 17 comments hardware
- ISSCC 2018: MIT’s low-power hardware crypto RISC-V IoT processor https://fuse.wikichip.org/news/1068/isscc-2018-mits-low-power-hardware-crypto-risc-v-iot-processor/ 3 comments hardware
- ISSCC 2018: Intel’s Skylake-SP Mesh and Floorplan https://fuse.wikichip.org/news/1017/isscc-2018-intels-skylake-sp-mesh-and-floorplan/ 8 comments hardware
- X-Gene 3 gets a second chance at Ampere with a new 32-core 16nm ARM processor https://fuse.wikichip.org/news/776/x-gene-3-gets-a-second-chance-at-ampere-with-a-new-32-core-16nm-arm-processor/ 9 comments hardware
- IEDM 2017: Sony’s 3-layer stacked CMOS image sensor technology https://fuse.wikichip.org/news/763/iedm-2017-sonys-3-layer-stacked-cmos-image-sensor-technology/ 10 comments hardware
- Eni fires up its supercomputer, breaks into the TOP500’s top ten, utilizing Intel's Skylake SP processors https://fuse.wikichip.org/news/746/eni-fires-up-their-supercomputer-breaks-into-the-top500s-top-ten/ 8 comments intel
- Esperanto exits stealth mode, aims at AI with a 4,096-core 7nm RISC-V monster https://fuse.wikichip.org/news/686/esperanto-exits-stealth-mode-aims-at-ai-with-a-4096-core-7nm-risc-v-monster/ 32 comments hardware
- Intel’s Total Memory Encryption, a new x86 extension for full memory encryption https://fuse.wikichip.org/news/634/intels-total-memory-encryption-a-new-x86-extension-for-full-memory-encryption/ 6 comments hardware
- Intel’s Total Memory Encryption, a new x86 extension for full memory encryption https://fuse.wikichip.org/news/634/intels-total-memory-encryption-a-new-x86-extension-for-full-memory-encryption/ 4 comments intel