Hacker News
- Formal Specification of the x86 Instruction Set Architecture [pdf] https://core.ac.uk/download/pdf/10697957.pdf 2 comments
- The BPF instruction set architecture is now RFC 9669 https://lwn.net/Articles/997002/ 10 comments
- Its time to design a new Instruction set architecture https://news.quelsolaar.com/2021/02/08/its-time-to-design-a-new-instruction-set-architecture/ 7 comments
- RISC++ Proposed Instruction Set Architecture (2012) http://arstechnica.com/civis/viewtopic.php?f=8&t=1186030 2 comments
- Loongson Technology develops its own CPU instruction set architecture https://www.tomshardware.com/news/loongson-technology-develops-its-own-cpu-instruction-set-architecture 34 comments
- A Complete Formal Semantics of x86-64 User-Level Instruction Set Architecture http://fsl.cs.illinois.edu/index.php/A_Complete_Formal_Semantics_of_x86-64_User-Level_Instruction_Set_Architecture 27 comments
- ForwardCom: Proposal for forward compatible instruction set architecture (2018) https://forwardcom.info/ 3 comments
- ForwardCom: Proposal for forward compatible instruction set architecture (2018) http://www.forwardcom.info 14 comments
- Design of the RISC-V Instruction Set Architecture [pdf] http://www.eecs.berkeley.edu/~waterman/papers/phd-thesis.pdf 48 comments
- Intel GPU Instruction Set Architecture Gets First Overhaul Since 2004 https://wccftech.com/intel-gpu-instruction-set-gets-first-massive-overhaul-for-intel-xe-architecture-since-2004/ 5 comments
- IBM has released the Power Architecture instruction set to the Linux Foundation https://www.eejournal.com/article/ibm-gives-away-powerpc-goes-open-source/ 136 comments
- Introducing Quil: A Practical Quantum Instruction Set Architecture https://medium.com/@rigetticomputing/introducing-quil-a-practical-quantum-instruction-set-architecture-a684f0590a0c#.vgbavkqvi 3 comments
- Clockhands: Rename-Free Instruction Set Architecture for Out-of-Order Processors https://dl.acm.org/doi/10.1145/3613424.3614272 5 comments
- Clockhands: Rename-free instruction set architecture for out-of-order processors https://dl.acm.org/doi/fullHtml/10.1145/3613424.3614272 34 comments
Lobsters
- Design of the RISC-V Instruction Set Architecture http://www.eecs.berkeley.edu/~waterman/papers/phd-thesis.pdf 2 comments assembly , hardware , pdf
- Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors https://dl.acm.org/doi/fullHtml/10.1145/3613424.3614272 4 comments hardware
- What can you do with an ISA (Instruction Set Architecture) specification? https://alastairreid.github.io/uses-for-isa-specs/ 2 comments programming
- AMD RDNA 1.0 Instruction Set Architecture https://gpuopen.com/compute-product/amd-rdna-1-0-instruction-set-architecture/ 14 comments hardware
- ZISC: Zero Instruction Set Computer Architecture http://www.kevindowd.com/zisc.txt 14 comments programming
- AMD: "RDNA4" Instruction Set Architecture Reference Guide https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna4-instruction-set-architecture.pdf 8 comments hardware
- "RDNA3" Instruction Set Architecture Reference Guide https://developer.amd.com/wp-content/resources/RDNA3_Shader_ISA_December2022.pdf 53 comments hardware
- IBM POWER Instruction Set Architecture Now Open Source https://www.infoq.com/news/2019/08/ibm-power-isa-open-source/ 3 comments opensource
- A Complete Formal Semantics of x86-64 User-Level Instruction Set Architecture http://fsl.cs.illinois.edu/index.php/a_complete_formal_semantics_of_x86-64_user-level_instruction_set_architecture 11 comments programming
- Design of the RISC-V Instruction Set Architecture [pdf] http://www.eecs.berkeley.edu/~waterman/papers/phd-thesis.pdf 55 comments linux
- Design of the RISC-V Instruction Set Architecture http://www.eecs.berkeley.edu/~waterman/papers/phd-thesis.pdf 40 comments programming
- The SUBLEQ URISC (Ultimate RISC) / OISC (One Instruction Set Computer) Architecture http://techtinkering.com/blog/?id=20 2 comments programming
- AMD RDNA™ 3.5 Instruction Set Architecture (ISA) reference guide is now available https://gpuopen.com/amd-rdna-3-5-isa/ 2 comments amd
- AMD RDNA™ 3.5 Instruction Set Architecture (ISA) reference guide is now available https://gpuopen.com/amd-rdna-3-5-isa/ 2 comments hardware
- AMD RDNA™ 3 Instruction Set Architecture (ISA) reference guide is now available https://gpuopen.com/rdna3-isa-guide-now-available/ 2 comments amd
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture https://mips.com/blog/migrating-the-cpu-ip-development-from-mips-to-risc-v-instruction-set-architecture/ 5 comments hardware
- RISC-V is a new instruction set architecture designed to support computer architecture research and education. http://riscv.org/ 22 comments programming
- IBM Demonstrates Commitment to Open Hardware Movement. IBM is opening the POWER Instruction Set Architecture (ISA). https://newsroom.ibm.com/2019-08-21-ibm-demonstrates-commitment-to-open-hardware-movement 5 comments programming
- Apple receives patent for processor including multiple dissimilar processor cores that implement different portions of instruction set architecture http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=9958932&OS=9958932&RS=9958932 12 comments hardware
- I can finally say that I've finished my very first big project as a CS Student. Took me about 4 months of research and implementation: An Instruction Set Simulator based on the RISC-V Architecture. (I've also added as many features as I could to make it more complete). Feedback is welcomed! https://github.com/vmmc2/vulcan 4 comments programming