High-Performance Spaceflight Computing (HPSC) Project Overview - NASA Technical Reports Server (NTRS) - discu.eu

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NASA's High Performance Spaceflight Computing (HPSC) Chiplet Architecture | Radiation Hardened | 32nm SOI | 8x A53 + 1 A53 + 2 R52 | 3 DDR channels + 4 SRAM/NVRAM/MRAM channels | 6 SRIO + 2 PCI + Ethernet, SpaceWire, Time Triggered Ethernet (TTE), SPI, UART, I2C, GPIO | [PDF Warning] https://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/20180007636.pdf 20 comments 13/1/2019 hardware

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Space-grade CPUs: How do you send more computing power into space? | Ars Technica https://arstechnica.com/science/2019/11/space-grade-cpus-how-do-you-send-more-computing-power-into-space/3/ 0 comments

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